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ISL5314 Datasheet

  • ISL5314

  • CommLink Direct Digital Synthesizer

  • 164.70KB

  • Intersil   Intersil 

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TM
ISL5314
Data Sheet
September 2001
File Number
4901.1
Direct Digital Synthesizer
The 14-bit ISL5314 provides a
complete Direct Digital Synthesizer
(DDS) system in a single 48-pin
LQFP package. A 48-bit Programmable Carrier NCO
(numerically controlled oscillator) and a high speed 14-bit
DAC (digital to analog converter) are integrated into a stand
alone DDS.
The DDS accepts 48-bit center and offset frequency control
information via a parallel processor interface. A 40-bit
frequency tuning word can also be loaded via an asynchronous
serial interface. Modulation control is provided by 3 external
pins. The PH0 and PH1 pins select phase offsets of 0, 90,
180 and 270 degrees, while the ENOFR pin enables or
zeros the offset frequency word to the phase accumulator.
The parallel processor interface has an 8-bit write-only data
input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe
(WR), and a Write Enable (WE). The processor can update
all registers simultaneously by loading a set of master
registers, then transfer all master registers to the slave
registers by asserting the UPDATE pin.
Features
鈥?125MSPS output sample rate with 5V digital supply
鈥?100MSPS output sample rate with 3.3V digital supply
鈥?14-bit digital-to-analog (DAC) with internal reference
鈥?Parallel control interface for fast tuning (50MSPS control
register write rate) and serial control interface
鈥?48-bit programmable frequency control
鈥?Offset frequency register and enable pin for fast FSK
鈥?Small 48-pin LQFP packaging
Applications
鈥?Programmable local oscillator
鈥?FSK, PSK modulation
鈥?Direct digital synthesis
鈥?Clock generation
Pinout
48-PIN LQFP (Q48.7X7A)
TOP VIEW
C3
C4
C5
C6
C7
DVDD
WR
DGND
WE
NC
A0
A1
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
34
3
33
4
32
5
31
6
ISL5314
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
1
Ordering Information
PART
NUMBER
ISL5314IN
ISL5314EVAL2
TEMP. RANGE
(
o
C)
-40 to 85
25
PACKAGE
48 LQFP
PKG. NO.
Q48.7X7A
C2
C1
C0
ENOFR
DGND
CLK
DVDD
RESET
UPDATE
COMPOUT
REFLO
REFIO
Evaluation Board
Block Diagram
C(7:0)
A(3:0)
WR
WE
UPDATE
SERIAL MODULATION
CONTROL
CONTROL
SDATA
SSYNC
SCLK
COMPOUT
MASTER
PHASE
ACCUM.
-
+
IN-
IN+
COMP1
COMP2
IOUTA
IOUTB
REFIO
REFLO
A2
A3
PH0
PH1
SSYNC
DVDD
SCLK
DGND
DGND
SDATA
DVDD
DGND
ENOFR
PH(1:0)
INT
REF
RESET
CLK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright 漏 Intersil Corporation 2000
CommLink鈩?is a trademark of Intersil Corporation.
FSADJ
COMP1
AGND
AGND
IOUTB
IOUTA
COMP2
AVDD
AGND
IN+
IN-
AGND
SINE
WAVE
ROM
鈭?/div>
14 BIT
DAC
SLAVE

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