鈥?/div>
LVPECL or LVCMOS/LVTTL Clock Input
150ps Maximum Targeted Output鈥搕o鈥揙utput Skew
Drives Up to 36 Independent Clock Lines
Maximum Output Frequency of 250MHz
32鈥揕ead TQFP Packaging
3.3V VCC Supply Voltage
FA SUFFIX
32鈥揕EAD TQFP PACKAGE
CASE 873A鈥?2
With a low output impedance (鈮?0鈩?, in both the HIGH and LOW logic
states, the output buffers of the MPC940 are ideal for driving series
terminated transmission lines. More specifically, each of the 18 MPC940
outputs can drive two series terminated 50鈩?transmission lines. With this
capability, the MPC940 has an effective fanout of 1:36 in applications
where each line drives a single load. With this level of fanout, the
MPC940 provides enough copies of low skew clocks for most high
performance synchronous systems.
The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC940 is fully 3.3V compatible. The 32鈥搇ead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32鈥搇ead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
6/97
漏
Motorola, Inc. 1997
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